Wired && Coded;

The picture below is an extract from Power-Supply Block Diagram of the official Agilex 3 Devkit. The FPGA requires multiple power supply levels: from 0.75V to 3.3V. Specification is found in altera document Power Management User Guide: Agilex™ 3 FPGAs… Continue Reading →

Theoretically, Agilex 3 FPGA does not require any external clock signals to load bitstream and to operate an (asynchronous) user design. However, in practice, all designs will need to supply some clock signals for use in EMIF (e.g. LPDDR4) or… Continue Reading →

Agilex 3 FPGA supports loading of the configuration bitstream by multiple methods. A method is selected by 3 strapping pins MSEL[2:0] (these are multi-purpose strapping pins). The common methods are: The recommended vendor of QSPI flash is Micron because of… Continue Reading →

Agilex 3 FPGA supports PCI-Express via its four GTS transceiver links. Each GTS physical link (tx+rx) supports up to 12.5Gbps transfer speed. On top of the GTS transceivers the FPGA implements hardened IPs for PCI-Express 3.0 x1-x2-x4, Ethernet 10 Gbe… Continue Reading →

Presently (2025) there are two perspective busses for connecting DRAM devices in embedded systems: The DDR3L supports traditional DDR multidrop bus topology with VTT termination and multiple memory devices sharing the address/control bus. The LPDDR4 is a completely different protocol… Continue Reading →

Ever since I attended the Altera FPGA workshMicronop featuring their new Agilex 3 device, I am thinking if Agilex could be the right FPGA to implement a general-purpose computation accelerator (i.e. a GPU) with a fast PCI-Express interface and a… Continue Reading →

Recently I attended Arrow’s Agilex 3 FPGA workshop, which promoted, obviously, the new Altera Agilex 3 FPGAs. In the workshop we completed lab tasks using also the new AXC3000 Starter Kit that features the Agilex 3 FPGA. At the end… Continue Reading →