AXC3000: Agilex FPGA Starter Kit

Recently I attended Arrow’s Agilex 3 FPGA workshop, which promoted, obviously, the new Altera Agilex 3 FPGAs. In the workshop we completed lab tasks using also the new AXC3000 Starter Kit that features the Agilex 3 FPGA. At the end of the day there was a quiz and so I happened to win one the AXC3000 boards for myself. In this article I present my first-look analysis of the board.

The Workshop

The workshop was officially themed as “AI-on-FPGA” although only a subset of lab tasks focused on machine-learning (AI) topics. Most topics were standard FPGA stuff, like completing a simple VHDL design, creating a Nios-V system, or analyzing the timing closure.
The complete workshop material including all projects is available in this online GIT repository:
https://github.com/ArrowElectronics/altera_workshops

The Agilex 3 FPGA

“Agilex” is the brand name of Altera’s line of their currently latest-and-greatest FPGAs. The top of the line are Agilex 9 and Agilex 7 FPGAs - these are very costly. The mid-range is Agilex 5 (released about a year ago), and the low-end is Agilex 3, which was released just this year.

The AXC3000 Starter Kit is equipped with the Agilex 3 FPGA device type A3CY100BM16AE7S, which sports the following main features:

  • A3C_100 => 100k Logic Elements (ALM) - quite a lot. In the lineup there are smaller devices 25k, 50k and 65k, and one larger device 135k.

  • 138 DSP blocks

  • 1.90 Peak INT8 TOPS

  • 4.47Mb internal memory

  • MIPI D-PHY interfaces

  • LVDS pairs at 1250 Mbps

  • AC3CY =>

    • Type Y = this device is missing the HPS (multicore CA55) processor subsystem => only the soft-core Nios-V will be available. On the other hand, the EMIF/MIPI are still available:

  • package M16A = 16 mm x 16 mm, 0.5 mm pitch. This package is upgradable to the largest 135k device:

Available Development Tools

One very nice feature of the Agilex 3 FPGA is the free-of-charge availability of the development tools - the Quartus Prime Pro. Not only the tool itself is free, but also all the built-in hard IP blocks in the FPGA are free to use without need of additional license! That is: when you buy a physical device, the license for all the IP in the device is already included in the price of the device and you don’t pay any additional just to use it in your code. Neat!

Built-in hard IP blocks include:

  • MIPI D-PHY (display & camera interface)

  • External memory interface: up to 2x LPDDR4 32-bit 2133Mbps

  • 10GbE MAC

  • PCIe 3.0 x4

  • Hard processor system (HPS) with multicore ARM: Dual-Core 64b A55 up to 800MHz

The Starter Kit AXC3000

The AXC3000 board is only 7 x 5cm and costs around 129 USD. It is powered from a USB-C connector which also provides a JTAG programming interface via an on-board FTDI device. Additional connectors include CRUVI high-speed (Samtec) connector with LVDS pairs and two pin-headers (not assembled) for low-speed signals (Arduino MKR compatible).

For this analysis I used a schematic of a slightly different board AXC5000, which seems to be identical up to the use of a larger but pin-compatible Agilex 5 device. This schematic is available online:
https://github.com/ArrowElectronics/Agilex-5/blob/main/images/AXE5000/SCH-TEI0181-01-MDE-2-A.PDF

Let’s analyze the board schematic by individual blocks:

Oscillator 25MHz

Oscillator for the FPGA is type Skyworks 510KCA25M0000CAG, 30ppm, 1.8V.

Bitstream QSPI-Flash

The QSPI-Flash for FPGA bitstream is Micron type MT25QU256ABA8E12-1SIT, 256Mbit, 1.8V. It works in the QSPI mode. Altera recommends Micron devices with minimal capacity 128Mbit as the typical size of bitstream image for 100k and 135k devices is 62Mbits (8MB).

CRUVI connector

The connector for the CRUVI-compatible high-speed interface is Samtec SS4-30-3.50-L-D-K-TR, 60 positions, 28Gbps. CRUVI is a standard for low-cost FPGA extension connectors and boards.

The CRUVI Samtec connector is mounted on the top side opposite of the USB-C port. It provides 12 LVDS pairs that support the MIPI D-PHY camera interface. One of the examples in the workshop material shows how to connect the OSRAM MIRA220 RGB camera to this board.

User RGB LEDs

There are two RGB LEDs. One is controlled by the FPGA (i.e. by the user code), the other from the USB FTDI chip. The RGB LEDs are Cree CLY6D-FKC-CK1N1D1BB7D3D3.

Accelerometer

There is a MEMS accelerometer LIS3DH from ST with an I2C interface. It is used in some of the example code.

No PCI-Express on the starter kit

The FPGA balls belonging to the GTS transceivers capable of implementing the PCI-Express interface are, sadly, not connected to any pins on the PCB:

USB-C Port

The USB-C connector provides 5V power input to the board, and supports the USB2.0 protocol for debugging functions (JTAG, UART). The VBUS (5V input) is configured in the “legacy” mode with the two pull-down 5k1 resistors on the CC1/CC2 lines. This means maximum 0.5A from the VBUS should be drawn.

The USB2 pins are connected to FTDI FT2232H USB/multi-protocol interface. The FTDI device provides two ports: port 1 is used in the MPSSE mode to implement a JTAG interface for the FPGA, and port 2 likely provides a simple UART interface (on BDBUS[0-1]).

A unique USB DeviceID is stored in EEPROM M93C66 attached to the FTDI chip so that a host PC loads appropriate drivers and recognizes the board as an FPGA programmer (Altera Blaster):

Finally there is a 12MHz oscillator 510CCA12M0000CAG also necessary for the FTDI USB PHY:

OSPI HyperRAM

Winbond HyperRAM W957D8NBRA4I with the OSPI (Octal-SPI) interface provides additional 128Mbit (16MB) of DRAM-like memory for the user. HyperRAM is internally a DRAM but with a QSPI or OSPI interface instead of a more typical parallel (DDRx) bus. The advantages are larger capacity and less signals (compared to SRAM) and easier handling by the host (compared to DRAM) since refresh cycles are handled completely inside of the HyperRAM device. The downside is smaller capacity and slower communication speed.

Power Supplies

The board and the FPGA requires following voltage levels generated from the input 5V:

  • 1.8V for IO, PLL

  • 1.2V for IO, SDM

  • 3.3V for HV-IO banks

  • 0.752V for FPGA core

  • adjustable 1.2V/1.3V for CRUVI IO

All these power rails are generated in five TDK DC/DC micro-modules FS1606-0600-AL, here showing schematic circuit of just one:

These modules are rated for up to 6A output and include telemetry and dynamic adjustment features over the I2C interface. The five modules are situated on the top side and occupy rather small space on the PCB:

Conclusion

Overall, the board is simple, yet offers some interesting possibilities. It is kind of a minimal design for the Agilex 3 FPGA. The recommended cost of the board 129 USD is also the cost of the used FPGA alone on mouser.

The good:

  • 100k device, only second to the largest 135k.

  • OSPI HyperRAM

  • CRUVI and GPIOs

The bad:

  • the FPGA does not include the HPS (ARM Cortex) subsystem. That is understandable, because HPS would also require LPDDR memory and additional flash for software, driving board cost much higher.

  • GTS transceivers (PCIe, ETH) not connected on the PCB