AGILA, and Her Test-board

AGILA will be a new open-source board with the Altera Agilex 3 FPGA, 2 GB to 8 GB
of LPDDR4 RAM and the PCI-Express interface. The Agilex 3 FPGA includes hard-IP support for PCI- Express interface up to Gen3 x4 and the LPDDR4 x32 up to 1066MHz (2133MT/s). The board form factor will be a low-profile PCI-Express card with the x4 edge connector. The upper edge of the board will be occupied by extension pin-header connectors. The board will also include a JTAG port and USB/JTAG interface for easy HDL development.

AGILA will very roughly look like this (the pic below is +- an AI hallucination, not finished design 🙃):

AGILA will enable me to do many exciting new experiments that are not so far possible with prior existing equipment, namely:

Experiment with the PCI-Express interface, including its software stack.
With 100k-gate FPGA, 2 to 8 GB of local DDR RAM, and the PCIe host interface, I will be able to experiment with compute accelerators. The obvious candidate is integer (matrix) linear algebra for LLM inference. (How difficult could it be?)
Extension connector for flex cable opens the possibility for a camera or display interface over MIPI.
Pin-header extensions could be used to create expansion with Gbit ethernet PHYs (network card), or display interfaces likes HDMI (Open Graphics Adapter, again?).
Experiment with the raw gigabit transceivers available in the FPGA. The board provides necessary signals on SMA connectors.

Why Agilex 3 FPGA?

Altera’s Agilex 3 FPGAs have many interesting features, but the last one is the most important for me:

100k to 135k logic elements in the two largest variants
affordable cost of a device around 130 USD/piece
GTS differential pairs up to 12.5Gbps with built-in (hard-core) implementation of PCI-Express Gen3 x4 (i.e. up to 32Gbps)
LPDDR4 memory interface x32 up to 2133Mbps
free-of-charge toolchain including free license for the built-in PCIe and LPDDR4 interfaces

The last item is the deal-maker: a free-of-charge license for the built-in PCIe and LPDDR4 interfaces. Although many other FPGAs on the market provide PCIe or DDR, it is locked behind a paid license which every developer must purchase in addition to the silicon chip itself. These licenses easily costs thousands of eur per year. This is a serious entry barrier for a DIY.

Her Test-board

As the first step in designing future AGILA board I need to test the intended power supplies (PSU), and the clocking and reset circuits.

Power Supplies for Agilex 3

As discussed previously here, Agilex 3 with LPDDR4 and PCIe requires 6 supply levels: 0.75V, 1.0V, 1.1V, 1.2V, 1.8V and 3.3V.

Previously I created designs with the 5V intermediate voltage. That is, the input power (5v to 24v) is first converted to 5V, which is the down-converted to all the necessary ASIC voltages (1v .. 3.3v). With Agilex 3 I modernize my dogma and will use the 3.3V level as the intermediate voltage. The input voltage, which is expected from 5V to 12V, will be converted to 3.3V, and then in the 2nd step to the lower voltages:

1st level:

5V to 12V -> 3.3V, 4A:
- TPS56424, 3V-17V Vin, 4A out.

2nd level – from the 3.3V:

0.75V – for FPGA core. Two options will be evaluated:
- /4A: TPS628304A with 2.2uH inductor — sufficient for the lower-tier FPGA (100k -7S (slowest device))
- /6A module: FS1606-0600-AL — necessary for 130k -6S (fastest) device.
1.0V – for GTS transceivers:
- /2A: TPS628302A with 470nH inductor
1.1V – for LPDDR4:
- /4A: TPS628304A with 470nH inductor – default, should be sufficient in all cases.
- /6A module: FS1606-0600-AL — alternative, ok in testboard but may skip in the real board.
1.2V – for SDM and support functions in the FPGA:
- /2A: TPS628302A with 470nH inductor
1.8V – for LPDDR4 and basic IO:
- /2A: TPS628302A with 470nH inductor
3.3V
- a load switch TPS22917DBV from the existing intermediate 3.3V.

As is usual, I want to measure the stability of all converters, check voltage levels and check the sequencing. Since I want to avoid performing these measurements on a board with costly FPGA I will validate the circuits in ‘Her Testboard’.

Clocking for Agilex 3

As analyzed previously here, we need multiple clocks for Agilex 3 to support LPDDR4 and PCIe interfaces:

100MHz single-ended @1.8V level for FPGA SDM functions
100MHz differential at the ‘True Differential 1.1V’ levels for FPGA LPDDR4
maybe additional 100MHz TrueDiff-1.1V for MIPI
maybe single-ended 100MHz clock for HVIO (1.8V) or HSIO banks (1.5V)

I settled on an architecture with a local 100MHz oscillator generating single-ended clock signal at 1V8, then a 1:4 clock distribution buffer to generate multiple copies of it (for SDM, HVIO), single-ended. One of the copies is fed into a differential (LPHCSL) clock distributor 1:4 which provides the additional diff. clocks for LPDDR4 and MIPI. Transformation from LPHCSL to Altera’s True-Diff-1V1 is handled by R/C networks.

I am quite sure that the designed clock network will basically work, but the values in the RC circuits must be checked and the signals measured. Therefore this circuit is implemented in ‘Her Testboard’.

Reset

For resetting Agilex 3 we need a power-on reset delay circuit that deactivates the SDM reset after the last power-supply converter is OK; this is straightforward.

In addition to the power-on reset I want the FPGA to be reset also by the PCIe Cold Reset, i.e. the signal PERST# going low. Once PERST# is released (high) the FPGA should start communicating over the PCIe in under 100ms. The problem is that FPGA bitstream configuration might take longer than 100ms. Therefore, I designed a derivation circuit which resets the FPGA for a brief moment just on the falling edge of PERST# and then it allows its configuration to proceed even as PERST# is still low. This trick should provide additional time, but the whole reset circuit must be checked in ‘Her Testboard’.

The Testing PCB

The picture below shows Kicad rendering of the testboard PCB for future AGILA.

The board will be manufactured by PCBWAY – www.pcbway.com:

Lets start a new quote and fill in the PCB parameters. In the first block we have to fill in the board size (99.15mm by 98.5mm), the number of pieces (5 is the minimum) and the number of layers (4). Since this is a test-board which will be populated by hand, I set board type to Single – No panel.

In the second block of parameters we are asked about the material. I leave the default FR4 and the standard thickness 1.6mm, which is OK for a PCIe card. (For comparision, an M.2 format requires the board thickness 0.8mm).

Next comes very important question about the minimum track width and the minimum spacing between tracks. The default is 6/6mil, which is 0.1524mm. However, this is slightly too big because of the USB-C connector footprint that I use which has the spacing just 0.1500mm. Therefore, the parameter Min track/spacing must be reduced to 5/5mil (0.127mm), which is OK.

The following block asks about the desired board base colour and printing colour. Here I leave the default green board and white text, which has the best performance anyway:

Then there are options regarding edge connectors and the overall surface finish. Here we must enable the Edge connector option because we have the PCI-Express edge ‘fingers’. The belling should be 20 degrees as is specified in the PCI-Express standard.

For the surface finish I select the HASL lead-free. Although for the PCI-Express this might not be the best option in a product, for a test-board this is perfectly acceptable and most cost effective:

In the final block we are asked the important question how to treat vias. The default is ‘tenting vias’ which means the vias are covered (closed) and not solderable (which is typically wanted). However, we are warned that with Gerber inputs the option here is not effective, but parameters in the files will be observed.