Agilex 3 FPGA supports loading of the configuration bitstream by multiple methods. A method is selected by 3 strapping pins MSEL[2:0] (these are multi-purpose strapping pins). The common methods are:
- MSEL[2:0]=111 => wait for JTAG download,
- MSEL[2:0]=011 => normal QSPI Flash download mode
- MSEL[2:0]=001 => “fast” QSPI Flash download mode – this just skips a 10ms wait before accessing QSPI flash which is normally part of the normal QSPI flash download mode. This could help with PCIe link-up requirements, but the design must ensure that the QSPI device is ready.
The recommended vendor of QSPI flash is Micron because of speed.
The configuration process is controlled by Secure Device Manager (SDM), a built-in tripple-redundant microcontroller, not user accessible, that provides authentication and other features. Firmware for SDM is part of the bitstream and it is added automatically by Quartus.
The picture below is part of the schematic of the Agilex 3 Devkit that shows the configuration and SDM pins:
JTAG pins (yellow) – shall be available on a connector for the Altera Blaster II programmer.
SDM Clock input (OSC_CLK_1) – although the FPGA has an internal clock, for advanced features (MIPI, PHYs) it is necessary to provide a stable external clock to this pin (i.e. 25/100/125MHz @ 1V8).
SDM_IO[0..15] – these are multi-purpose pins. They are configured in Quartus in the Device and Pin Options. The configuration is part of the SDM firmware, which is the first section of the bitstream (loaded and activated before the rest of the bitstream).
The SDM_IO[] include QSPI Flash interface pins (marked green above), MSEL strapping, Factory Default Reset, and the Config-Done pin.
Finally, the SDM_NCONFIG is the FPGA Reset input, which re-starts the configuration process. The signal SDM_NSTATUS (should be pulled high) is an acknowledge signal for the NCONFIG.
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