Processor Low-power Optimizations in PIP-Watch

Processor Power

The PIP-Watch is a battery-powered device that will be continuously on, hence the average power consumption is one of the most important engineering aspects.

In this post I will go through two simple steps of optimizing CPU power – sleep modes and lowering the clock frequency. In a next separate post we will look into Bluetooth module power.

Full Steam Ahead!

The CPU in PIP-Watch is STM32F103RC from ST-Microelectronics. By selecting PLL division and multiplication factors, the CPU core can be run at up to 72MHz clock. However, at this speed it draws huge amounts of power. The oscilogram below shows that it (actually the complete PIP-Watch) draws 40mA of current continuously. The PIP-Watch is equipped with Nokia BL-4C Li-On battery with the capacity 860mAh. At 40mA draw the battery would be flat after only 21 hours, but probably even earlier. The smartwatch would not last even a day!

CPU on full steam: 72MHz clock, no sleeping.
CPU on full steam: 72MHz clock, no sleeping.

 

Sleeping When Idle

The CPU firmware in PIP-Watch operates the FreeRTOS real-time operating system. The OS allows nice separation of different functions the device has to perform, – like redrawing a screen, checking battery, communicating via Bluetooth, – into tasks. When all tasks are waiting for some future event, the OS runs a so-called ‘idle’ task. Normally this ‘idle’ task just performs an infinite loop, burning CPU cycles (and power!) until any useful task wakes up to do something more meaningful.

FreeRTOS has a hook function named vApplicationIdleHook() which is called whenever the idle task is reentered. Task switching is controlled by interrupts, mainly by a timer interrupt. Instead of waiting for an interrupt in a loop, like the default idle task does, we will use a special CPU instruction WFI (Wait-For-Interrupt). This instruction stops the CPU core clock until an interrupt comes.

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/* FreeRTOS: User defined function executed from within the idle task. */
void vApplicationIdleHook( void )
{
    /* Activate the sleep mode - wait for next interrupt. */
    __WFI();
}
/* FreeRTOS: User defined function executed from within the idle task. */
void vApplicationIdleHook( void )
{
    /* Activate the sleep mode - wait for next interrupt. */
    __WFI();
}

The result is no degradation or alteration of the device functionality, as we are sleeping when there is nothing to do anyway, and a significant reduction of power consumption.

As shown in an oscilogram below, the baseline power consumption when the CPU core sleeps is only 15mA, and it shortly peaks to about 19mA every 1ms. The 1ms interval comes from the system timer interrupt which is used by FreeRTOS for task scheduling.

CPU sleeps when idle, 72MHz clock.
CPU sleeps when idle, 72MHz clock.

The picture below is a detail of one peak. The peak is about 20us wide.

Detail of one CPU peakm 72MHz clock.
Detail of one CPU peakm 72MHz clock.

 

Slowing Down the CPU

Power consumption in CPUs (or any digital logic) scales approximately linearly with clock frequency. By reducing the clock frequency the CPU runs slower and requires less power. Because we are not doing any heavy computation in PIP-Watch the slow-down will not affect functionality in any perceivable way.

The oscilogram below shows the current consumption with the CPU clock frequency reduced from 72MHz to 8MHz. Idle current is about 6mA, and it peaks to 10mA every 1ms. At this rate the battery will last (theoretically) up to 4 days, which is acceptable for now.

Slow CPU clock 8MHz, and sleeping when idle.
Slow CPU clock 8MHz, and sleeping when idle.

 

Avg current Estimated battery life
CPU 72MHz 40mA 21h
Sleep when idle 15mA 57h
Slow clock and sleep when idle 6mA 143h = 5 days

 

Measurement Method

Current was measured as a voltage drop across a 1-ohm  shunt resistor. The resistor creates a drop of 1mV per 1mA of current. See  photo in the post’s header. Watch this Dave Jones’ video on oscilloscope power measurement.

The shunt resistor is installed between battery negative pole and the system ground (GND). Oscilloscope probe must be connected to the negative battery terminal and the probe ground lead to the system ground (GND). The disadvantage of this method is that scope picture is inverted (zero at the top), unless you use a special inversion function on your scope instrument.

The big advantage of this method is that the battery will not blow up when you connect your JTAG programmer to PIP-Watch simultaneously with a scope probe as a result of a short-circuit via mains ground. Remember: the oscilloscope ground lead is connected through to mains protective wire, as well as your PC case, the USB ground signal, and the JTAG programmer ground signal. So all these signals must be kept at the same potential, with no current flowing through, otherwise you measure garbage and things start to smoke!

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