The PIP-Watch is a battery-powered device that will be continuously on, hence the average power consumption is one of the most important engineering aspects.
In this post I will go through two simple steps of optimizing CPU power – sleep modes and lowering the clock frequency. In a next separate post we will look into Bluetooth module power.
The printed circuit boards for PIP-Watch Zero came from Pragoboard fab on Friday 12 Sept. I ordered three pieces because the cost is practically identical as for two or one.
On Saturday I assembled one board, and on Sunday I tested it and started working on firmware. I had some problems with PLL in the microcontroller – the CPU hard-resetted the instant the PLL was enabled. Eventually I found a bad solder joint on one of the CPU’s power supply pins.
So far I tested the CPU & JTAG, the eInk EPD display, Bluetooth modem access (but not the BT communication itself), and LEDs. I had issues with bad solder joints (both shorts and cold joints) because the PCB footprint for the CPU (the LQFP64 package) was apparently designed for the reflow process, and it is not suitable for hand soldering. Silly KiCAD libraries!
Measuring crystal frequencies:
Schematic [PDF], BOM, and PCB layout for my PIP-Watch “Zero” was completed during this week. Layout data was sent to a local PCB fab – pragoboard.cz. The board should be ready and shipped during the next week.
The PCB is is 80mm*35mm. The top side is dedicated to the EPD display, battery (underneath the display), 3 push-buttons and 4 LEDs. The bottom side carries all the main electronics – processor, bluetooth modem, display driver, and power source.
All design files are in the project repository.